1. Field of the Invention
This invention relates generally to battery operated integrated circuits, and, more particularly, to reset circuits used in battery operated integrated circuits.
2. Description of the Related Art
As electronic devices have become increasingly sophisticated, a single device may employ multiple general processing units. For example, in cordless telephones that also contain voice messaging, caller identification, and other sophisticated options, multiple processors may be used, such as a microcontroller and a digital signal processor (DSP). The processors may not be arranged in a master-slave relationship, but rather, may be configured to work together to separately control different functions within the system. For example, the microcontroller may be involved in administrative tasks, whereas the DSP may control more sophisticated tasks, such as voice compression, voice recognition, voice message storage, and the like.
Since these different processors are performing functions of significantly different sophistication and priority, their response time to external, asynchronous events, such as interrupts may vary significantly. For example, an external event, such as an interrupt generated by a low-battery detection circuit, may cause the microcontroller to virtually immediately enter a reset mode without adversely impacting the operation of the telephone system, because either the microcontroller has sufficient time to complete its current task before being reset, or it is not critical that the microcontroller complete its current task. On the other hand, the DSP may not be able to complete the relatively sophisticated tasks on which it is currently working before the interrupt causes it to shut down its operation. Where the DSP is performing tasks that may be critical to its continued operation, discontinuing these tasks before they are completed may prevent the telephone system from reinitializing in its proper state after the low battery condition has been corrected. For example, the DSP may be updating or writing a serial flash device at the time of the low-battery interrupt. The data being written may be irretrievably lost if the process is interrupted.
Heretofore, electronic devices have typically responded to external, asynchronous events, such as a low battery interrupt, by forcing the device to immediately enter a low power reset mode by turning off the system clock. Thus, as discussed above, in devices where the processor is performing relatively sophisticated tasks, immediately shutting down its system clock may result in loss of data, or more significantly, may prevent the system from properly restarting when the low battery condition is corrected.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided. The method is used to control a reset operation of a device. The method includes delivering a first signal indicating that a voltage supply has fallen below a first preselected level. The device receives the first signal and delivers a second signal acknowledging that the device is prepared to enter a reset mode of operation. Thereafter, a reset signal is delivered to the device to cause the device to enter a reset mode of operation in response to receiving the first signal and the acknowledging signal.
In another aspect of the present invention, a system is provided. The system includes a detector, first and second processors, and a reset circuit. The detector is capable of delivering a first signal in response to detecting a preselected condition. The first processor is adapted to receive the first signal and deliver an acknowledge signal indicating that the first processor will enter a reset mode of operation in response to receiving a reset signal. The second processor is adapted to enter the reset mode of operation in response to receiving the first signal. The reset circuit is adapted to deliver a reset signal to the first processor in response to receiving the first signal and the acknowledge signal.
In another aspect of the present invention, an apparatus for controlling a reset operation of a device is provided. The apparatus includes a logic circuit and a timer. The logic circuit is adapted to deliver a reset signal to the device in response to receiving a low battery signal and an acknowledge signal from the device indicating that the device has received the low battery signal and is prepared to enter the reset mode of operation. The timer is adapted to deliver a clock disable signal to a system clock a preselected period of time after receiving the low battery and acknowledge signals.
In yet another aspect of the present invention, a system is provided. The system includes a detector, a reset circuit and a processor. The detector is capable of delivering a first signal in response to detecting a preselected condition. The processor is adapted to receive the first signal and deliver an acknowledge signal indicating that the first processor will enter a reset mode of operation in response to receiving a reset signal. The reset circuit is adapted to deliver a reset signal to the processor in response to receiving the first signal and the acknowledge signal.